Embedded silicon germanium (SiGe) has recently been used as the source/drain material to boost channel hole mobility (due to the stress induced by lattice mismatch). Nickel platinum (NiPt) silicide is the standard contact metal to the SiGe, however NiPt—SiGe reaction under normal rapid thermal anneal (RTA) results in bad interface morphology (silicide spikes).
Silicide spikes into the SiGe source/drain may cause severe stress loss or junction leakage. This bad interface morphology issue becomes even worse when the percentage of germanium (Ge) is increased.
Conventional approaches to deal with the problem include using a silicon (Si) or SiGe cap layer with a lower percentage of Ge in order to improve the surface morphology. Namely, the cap layer reacts with the NiPt to form the NiSi, thus avoiding the interface morphology problem. However, employing a cap layer in a fabrication process flow increases both production complexity and cost.
Therefore, techniques that avoid bad interface morphology in SiGe source/drain contact formation without introducing the complexity and cost of using a cap layer would be desirable.